Consistency: fix external-link syntax, heading case and wikilink form |
Add a lead sentence |
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| （未顯示同一使用者於中間所作的 1次修訂） | |||
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The '''ESP32''' is a dual-core Xtensa SoC with Wi-Fi and Bluetooth. These notes cover its pin assignments and the constraints on them. | |||
== pin == | == pin == | ||
== [[Application - AWS IoT]] | |||
The pin numbering below is for the ESP32-WROOM-32 module as exposed on a | |||
DevKitC-style board. Other modules expose a different subset. | |||
* Core: Xtensa LX6 dual-core, up to 240 MHz, 520 KB SRAM | |||
* Radio: Wi-Fi 802.11 b/g/n, Bluetooth 4.2 BR/EDR and BLE | |||
* 34 GPIOs, numbered 0-19, 21-23, 25-27 and 32-39 | |||
{| class="wikitable" | |||
! Function !! Pins !! Note | |||
|- | |||
| Do not use || GPIO6-GPIO11 || wired to the module's own SPI flash | |||
|- | |||
| Input only || GPIO34-GPIO39 || no output driver, no internal pull-up/pull-down | |||
|- | |||
| Strapping || GPIO0, 2, 5, 12, 15 || sampled at reset, affects boot mode | |||
|- | |||
| UART0 || TX GPIO1, RX GPIO3 || the console used by the bootloader | |||
|- | |||
| I2C (default) || SDA GPIO21, SCL GPIO22 || remappable | |||
|- | |||
| VSPI || MOSI 23, MISO 19, CLK 18, CS 5 || | |||
|- | |||
| HSPI || MOSI 13, MISO 12, CLK 14, CS 15 || | |||
|- | |||
| ADC1 || GPIO32-GPIO39 || usable while Wi-Fi is active | |||
|- | |||
| ADC2 || GPIO0, 2, 4, 12-15, 25-27 || '''unavailable while Wi-Fi is active''' | |||
|- | |||
| DAC || GPIO25, GPIO26 || 8-bit | |||
|- | |||
| Touch T0-T9 || GPIO4, 0, 2, 15, 13, 12, 14, 27, 33, 32 || | |||
|} | |||
* GPIO12 (MTDI) is read at reset to select the flash voltage; holding it high can | |||
stop the board booting. | |||
* Almost every peripheral is routed through the GPIO matrix, so the UART, I2C and | |||
SPI assignments above are defaults rather than fixed pins. | |||
== Related projects == | |||
* [[Application - AWS IoT]] | |||
[[Category:Boards and SoCs]] | [[Category:Boards and SoCs]] | ||
2026年8月23日 (日) 17:57的最新修訂
The ESP32 is a dual-core Xtensa SoC with Wi-Fi and Bluetooth. These notes cover its pin assignments and the constraints on them.
pin
The pin numbering below is for the ESP32-WROOM-32 module as exposed on a DevKitC-style board. Other modules expose a different subset.
- Core: Xtensa LX6 dual-core, up to 240 MHz, 520 KB SRAM
- Radio: Wi-Fi 802.11 b/g/n, Bluetooth 4.2 BR/EDR and BLE
- 34 GPIOs, numbered 0-19, 21-23, 25-27 and 32-39
| Function | Pins | Note |
|---|---|---|
| Do not use | GPIO6-GPIO11 | wired to the module's own SPI flash |
| Input only | GPIO34-GPIO39 | no output driver, no internal pull-up/pull-down |
| Strapping | GPIO0, 2, 5, 12, 15 | sampled at reset, affects boot mode |
| UART0 | TX GPIO1, RX GPIO3 | the console used by the bootloader |
| I2C (default) | SDA GPIO21, SCL GPIO22 | remappable |
| VSPI | MOSI 23, MISO 19, CLK 18, CS 5 | |
| HSPI | MOSI 13, MISO 12, CLK 14, CS 15 | |
| ADC1 | GPIO32-GPIO39 | usable while Wi-Fi is active |
| ADC2 | GPIO0, 2, 4, 12-15, 25-27 | unavailable while Wi-Fi is active |
| DAC | GPIO25, GPIO26 | 8-bit |
| Touch T0-T9 | GPIO4, 0, 2, 15, 13, 12, 14, 27, 33, 32 |
- GPIO12 (MTDI) is read at reset to select the flash voltage; holding it high can
stop the board booting.
- Almost every peripheral is routed through the GPIO matrix, so the UART, I2C and
SPI assignments above are defaults rather than fixed pins.